Digital circuits play an increasingly important role in a variety of devices such as digital cameras, cellular telephones, digital music players and digital video disk (DVD) players, portable computing devices and digital television sets.
Further proliferation of digital devices will be aided by continued decreasing costs, as exemplified by the increasing density of transistors packed on to a given area of silicon die. Reducing the area consumed by an integrated circuit (IC) formed on a silicon die is thus an important factor in lowering costs. Moreover, smaller die sizes are desirable as they increase the yield from a given silicon wafer. Performance is also typically increased as electrical interconnections between various blocks in the integrated circuit are shortened.
Flip-flops are among the basic building blocks used in digital circuits. Flip-flops are used in sequential circuits to store state information. State transitions occur at predetermined times, typically defined by rising or falling edges of a clock signal.
A typical flip-flop has a data input, a clock input and a data output. Data at the data input is sampled, and provided at the output, at a rising or falling clock edge. Typically, to reliably sample the input signal a flip-flop requires the input signal level to be stable for a defined minimum duration before a clock edge (used for sampling the input data). This duration is called the setup-time. Similarly, flip-flops also require the sampled input signal to remain stable after the clock edge, for a defined duration. This duration is called the hold-time. If the input signal level is sampled before the setup-time, a setup-time violation occurs. Similarly, if the input signal changes before the required minimum duration following the clock edge used for sampling, a hold-time violation occurs.
If a circuit is to operate reliably, neither setup-time violations nor hold-time violations should occur. As can be appreciated, in high speed circuits utilizing a clock signal with high frequency, it is often challenging to ensure that no setup-time or hold-time violations occur. Hold violations often occur in pipeline stages of a circuit that have no combinatorial logic between them. Without combinational logic, the propagation delay of signals between stages is negligible.
A typical application where hold-time violations may be observed is in the testing of integrated circuit chips. One of the more popular methods for testing integrated circuits is the scan test. In scan tests, flip-flops in the circuit are connected together to effectively form a large shift register. A multiplexer at an input of a flip-flop is set to select either a scan test input during testing, or ordinary data input, during normal operation. A circuit block including a multiplexer and a flip-flop, with the multiplexer having a scan input, a normal data input, and an output interconnected to the input of a flip-flop, is called a scan flip-flop or scan cell.
During scan tests, the combinatorial blocks in a circuit may be bypassed as scan test data is shifted into pipeline stages made of scan flip-flops. Scan flip-flops so operated have no combinatorial logic connected between them, and signals propagate from one stage to another very quickly, potentially causing hold-time violations.
To counter hold-time violations, buffers are often inserted between scan flip-flops. Unfortunately, inserting buffers causes the area required by the resulting integrated circuit to increase, thereby increasing costs.
Accordingly, there is a need for a flip-flop that is better suited to achieve hold-time requirements on scan input and reduces the need for inserted buffers.